an-thony350/Mandelbros
GitHub repository with 6 stars and 0 forks.
Language: SystemVerilog
GitHub repository with 6 stars and 0 forks.
Language: SystemVerilog
Trending score 0.10, freshness score 0.93, stars gained +0, forks gained +0.
2026-06-15: 6 stars and 0 forks.
OpenTitan: Open source silicon root of trust
GitHub repository with 3,461 stars and 1,048 forks.
Trending score: 2.26; stars gained: +11; forks gained: +0.
Language: SystemVerilog
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 49 stars and 7 forks.
Trending score: 1.05; stars gained: +7; forks gained: +0.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 406 stars and 108 forks.
Trending score: 1.03; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
GitHub repository with 19 stars and 0 forks.
Trending score: 0.60; stars gained: +2; forks gained: +0.
Language: SystemVerilog
EECE26 - Digital IC Design and Verification Graduation Project | Source Code
GitHub repository with 6 stars and 0 forks.
Trending score: 0.42; stars gained: +1; forks gained: +0.
Language: SystemVerilog
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
GitHub repository with 544 stars and 524 forks.
Trending score: 0.42; stars gained: +0; forks gained: +2.
Language: SystemVerilog
OpenTitan: Open source silicon root of trust
GitHub repository with 3,461 stars and 1,048 forks.
Trending score: 2.26; stars gained: +11; forks gained: +0.
Language: SystemVerilog
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 49 stars and 7 forks.
Trending score: 1.05; stars gained: +7; forks gained: +0.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 406 stars and 108 forks.
Trending score: 1.03; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
GitHub repository with 19 stars and 0 forks.
Trending score: 0.60; stars gained: +2; forks gained: +0.
Language: SystemVerilog
EECE26 - Digital IC Design and Verification Graduation Project | Source Code
GitHub repository with 6 stars and 0 forks.
Trending score: 0.42; stars gained: +1; forks gained: +0.
Language: SystemVerilog
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
GitHub repository with 544 stars and 524 forks.
Trending score: 0.42; stars gained: +0; forks gained: +2.
Language: SystemVerilog