chenyuliu577-cyber/jyd-rv32i-fpga-core
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 51 stars and 8 forks.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga, hardware-design, riscv, rv32i, systemverilog