fpgasystems/Coyote

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

GitHub repository with 371 stars and 104 forks.

Language: SystemVerilog

Topics: fpga, rdma, tcp, virtualization, gpu, networking, hardware-acceleration

Open provider repository

24h trend summary

Trending score 1.08, activity score 1.06, stars gained +8, forks gained +1.

Latest metric snapshot

2026-06-02: 371 stars and 104 forks.

Similar repositories

  1. 1. fpgasystems/Coyote

    Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

    GitHub repository with 371 stars and 104 forks.

    Trending score: 1.08; stars gained: +8; forks gained: +1.

    Language: SystemVerilog

    Topics: fpga, rdma, tcp, virtualization, gpu, networking

Trending in SystemVerilog

  1. 1. fpgasystems/Coyote

    Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

    GitHub repository with 371 stars and 104 forks.

    Trending score: 1.08; stars gained: +8; forks gained: +1.

    Language: SystemVerilog

    Topics: fpga, rdma, tcp, virtualization, gpu, networking

  2. 2. lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    GitHub repository with 3,427 stars and 1,035 forks.

    Trending score: 0.61; stars gained: +1; forks gained: +3.

    Language: SystemVerilog

  3. 3. pavona/pavona

    A library of modular, tapeout-proven, and secure-by-default open silicon blocks

    GitHub repository with 60 stars and 13 forks.

    Trending score: 0.53; stars gained: +2; forks gained: +1.

    Language: SystemVerilog

  4. 4. xlsynth/bedrock-rtl

    High quality and composable RTL libraries in SystemVerilog

    GitHub repository with 33 stars and 5 forks.

    Trending score: 0.11; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: hardware, rtl, verilog, bazel-rules, chips

  5. 5. chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    GitHub repository with 378 stars and 94 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

  6. 6. rohtakpat314/riscvcpu

    Single-cycle RISC-V 32-bit CPU

    GitHub repository with 9 stars and 0 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

Trending topic: fpga

  1. 1. fpgasystems/Coyote

    Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

    GitHub repository with 371 stars and 104 forks.

    Trending score: 1.08; stars gained: +8; forks gained: +1.

    Language: SystemVerilog

    Topics: fpga, rdma, tcp, virtualization, gpu, networking

  2. 2. vicharak-in/shrike

    Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.

    GitHub repository with 446 stars and 60 forks.

    Trending score: 0.68; stars gained: +4; forks gained: +0.

    Language: Verilog

    Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike

  3. 3. stnolting/neorv32

    🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    GitHub repository with 2,123 stars and 343 forks.

    Trending score: 0.65; stars gained: +3; forks gained: +1.

    Language: VHDL

    Topics: risc-v, soft-core, vhdl, fpga, soc, microcontroller

  4. 4. verilog-to-routing/vtr-verilog-to-routing

    Verilog to Routing -- Open Source CAD Flow for FPGA Research

    GitHub repository with 1,238 stars and 444 forks.

    Trending score: 0.53; stars gained: +2; forks gained: +1.

    Language: C++

    Topics: vtr, fpga, cad, verilog, placement, routing

  5. 5. whatchamacallem/libhatchet

    libhatchet is a fast compiling lightweight C17/C++20 bespoke alternative to the C++ standard library designed for cross-compilation to resource-constrained targets like DSPs, FPGAs, ASICs or WebAssembly.

    GitHub repository with 15 stars and 0 forks.

    Trending score: 0.50; stars gained: +2; forks gained: +0.

    Language: C++

    Topics: embedded, embedded-systems, cross-compile, google-test, asic, dsp

  6. 6. siliconcompiler/siliconcompiler

    Modular hardware build system

    GitHub repository with 1,164 stars and 127 forks.

    Trending score: 0.49; stars gained: +2; forks gained: -1.

    Language: Python

    Topics: asic, cmos, eda, fpga, hls, make