AbdallahMoSalah/UCIe-3.0-PHY-layer

24h trend summary

Trending score 0.42, freshness score 0.95, stars gained +1, forks gained +0.

Latest metric snapshot

2026-06-15: 6 stars and 0 forks.

Similar repositories

1. 1. lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   GitHub repository with 3,461 stars and 1,048 forks.

   Trending score: 2.26; stars gained: +11; forks gained: +0.

   Language: SystemVerilog

2. 2. chenyuliu577-cyber/jyd-rv32i-fpga-core

   Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.

   GitHub repository with 50 stars and 7 forks.

   Trending score: 1.05; stars gained: +7; forks gained: +0.

   Language: SystemVerilog

   Topics: computer-architecture, contest, cpu, digital-design, education, fpga

3. 3. fpgasystems/Coyote

   Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

   GitHub repository with 407 stars and 108 forks.

   Trending score: 1.03; stars gained: +0; forks gained: +0.

   Language: SystemVerilog

   Topics: fpga, rdma, tcp, virtualization, gpu, networking

4. 4. srg320/Arcade-PsikyoSH2_MiSTer

   GitHub repository with 19 stars and 0 forks.

   Trending score: 0.60; stars gained: +2; forks gained: +0.

   Language: SystemVerilog

5. 5. Omie2806/gpu

   GitHub repository with 27 stars and 1 forks.

   Trending score: 0.55; stars gained: +1; forks gained: +0.

   Language: SystemVerilog

6. 6. AbdallahMoSalah/UCIe-3.0-PHY-layer

   EECE26 - Digital IC Design and Verification Graduation Project | Source Code

   GitHub repository with 6 stars and 0 forks.

   Trending score: 0.42; stars gained: +1; forks gained: +0.

   Language: SystemVerilog

Trending in SystemVerilog

1. 1. lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   GitHub repository with 3,461 stars and 1,048 forks.

   Trending score: 2.26; stars gained: +11; forks gained: +0.

   Language: SystemVerilog

2. 2. chenyuliu577-cyber/jyd-rv32i-fpga-core

   Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.

   GitHub repository with 50 stars and 7 forks.

   Trending score: 1.05; stars gained: +7; forks gained: +0.

   Language: SystemVerilog

   Topics: computer-architecture, contest, cpu, digital-design, education, fpga

3. 3. fpgasystems/Coyote

   Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

   GitHub repository with 407 stars and 108 forks.

   Trending score: 1.03; stars gained: +0; forks gained: +0.

   Language: SystemVerilog

   Topics: fpga, rdma, tcp, virtualization, gpu, networking

4. 4. srg320/Arcade-PsikyoSH2_MiSTer

   GitHub repository with 19 stars and 0 forks.

   Trending score: 0.60; stars gained: +2; forks gained: +0.

   Language: SystemVerilog

5. 5. Omie2806/gpu

   GitHub repository with 27 stars and 1 forks.

   Trending score: 0.55; stars gained: +1; forks gained: +0.

   Language: SystemVerilog

6. 6. AbdallahMoSalah/UCIe-3.0-PHY-layer

   EECE26 - Digital IC Design and Verification Graduation Project | Source Code

   GitHub repository with 6 stars and 0 forks.

   Trending score: 0.42; stars gained: +1; forks gained: +0.

   Language: SystemVerilog