openhwgroup/cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

GitHub repository with 543 stars and 523 forks.

Language: SystemVerilog

Open provider repository

Latest metric snapshot

2026-06-05: 543 stars and 523 forks.

Similar repositories

  1. 1. fpgasystems/Coyote

    Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

    GitHub repository with 371 stars and 104 forks.

    Trending score: 1.08; stars gained: +8; forks gained: +1.

    Language: SystemVerilog

    Topics: fpga, rdma, tcp, virtualization, gpu, networking

  2. 2. lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    GitHub repository with 3,427 stars and 1,035 forks.

    Trending score: 0.61; stars gained: +1; forks gained: +3.

    Language: SystemVerilog

  3. 3. chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    GitHub repository with 378 stars and 94 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

  4. 4. XuanTongYao/XT_RISC-V_Soc

    一个极其简易的RV32I指令集单核MCU，用户级与特权级支持，仅运行机器模式。

    GitHub repository with 60 stars and 6 forks.

    Trending score: 0.04; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

  5. 5. baochip/baochip-1x

    Baochip 1x Silicon

    GitHub repository with 360 stars and 32 forks.

    Trending score: 0.04; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

  6. 6. amoslee2026/Babel

    AI-native Chiplet design flow based on open-source EDA toolchain

    GitHub repository with 25 stars and 3 forks.

    Trending score: 0.04; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

Trending in SystemVerilog

  1. 1. fpgasystems/Coyote

    Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

    GitHub repository with 371 stars and 104 forks.

    Trending score: 1.08; stars gained: +8; forks gained: +1.

    Language: SystemVerilog

    Topics: fpga, rdma, tcp, virtualization, gpu, networking

  2. 2. lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    GitHub repository with 3,427 stars and 1,035 forks.

    Trending score: 0.61; stars gained: +1; forks gained: +3.

    Language: SystemVerilog

  3. 3. chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    GitHub repository with 378 stars and 94 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

  4. 4. XuanTongYao/XT_RISC-V_Soc

    一个极其简易的RV32I指令集单核MCU，用户级与特权级支持，仅运行机器模式。

    GitHub repository with 60 stars and 6 forks.

    Trending score: 0.04; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

  5. 5. baochip/baochip-1x

    Baochip 1x Silicon

    GitHub repository with 360 stars and 32 forks.

    Trending score: 0.04; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

  6. 6. amoslee2026/Babel

    AI-native Chiplet design flow based on open-source EDA toolchain

    GitHub repository with 25 stars and 3 forks.

    Trending score: 0.04; stars gained: +0; forks gained: +0.

    Language: SystemVerilog