srg320/Arcade-PsikyoSH2_MiSTer
GitHub repository with 14 stars and 0 forks.
Language: SystemVerilog
GitHub repository with 14 stars and 0 forks.
Language: SystemVerilog
Trending score 0.83, activity score 0.22, stars gained +5, forks gained +0.
2026-06-13: 14 stars and 0 forks.
Verilator open-source SystemVerilog simulator and lint system
GitHub repository with 3,683 stars and 834 forks.
Trending score: 1.77; stars gained: +7; forks gained: +1.
Language: SystemVerilog
Topics: compilers, cpp, rtl, system-verilog, systemc, verilator
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 32 stars and 6 forks.
Trending score: 0.95; stars gained: +8; forks gained: +5.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
GitHub repository with 14 stars and 0 forks.
Trending score: 0.83; stars gained: +5; forks gained: +0.
Language: SystemVerilog
A VVC/H.266 screen content encoder in hardware and software.
GitHub repository with 7 stars and 0 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 95 forks.
Trending score: 0.19; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing
Verilator open-source SystemVerilog simulator and lint system
GitHub repository with 3,683 stars and 834 forks.
Trending score: 1.77; stars gained: +7; forks gained: +1.
Language: SystemVerilog
Topics: compilers, cpp, rtl, system-verilog, systemc, verilator
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 32 stars and 6 forks.
Trending score: 0.95; stars gained: +8; forks gained: +5.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
GitHub repository with 14 stars and 0 forks.
Trending score: 0.83; stars gained: +5; forks gained: +0.
Language: SystemVerilog
A VVC/H.266 screen content encoder in hardware and software.
GitHub repository with 7 stars and 0 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 95 forks.
Trending score: 0.19; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing