tmssngr/z8verilog
Zilog Z8 softcore in verilog
GitHub repository with 8 stars and 1 forks.
Language: SystemVerilog
Topics: fpga, sipeed-tang-nano-9k, tang-nano-9k, verilog
Zilog Z8 softcore in verilog
GitHub repository with 8 stars and 1 forks.
Language: SystemVerilog
Topics: fpga, sipeed-tang-nano-9k, tang-nano-9k, verilog
2026-06-05: 8 stars and 1 forks.
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
OpenTitan: Open source silicon root of trust
GitHub repository with 3,427 stars and 1,035 forks.
Trending score: 0.61; stars gained: +1; forks gained: +3.
Language: SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 94 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: compliance-testing, hdl, rtl, symbiflow, systemverilog, verilog
一个极其简易的RV32I指令集单核MCU,用户级与特权级支持,仅运行机器模式。
GitHub repository with 60 stars and 6 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Baochip 1x Silicon
GitHub repository with 360 stars and 32 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
AI-native Chiplet design flow based on open-source EDA toolchain
GitHub repository with 25 stars and 3 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
libhatchet is a fast compiling lightweight C17/C++20 bespoke alternative to the C++ standard library designed for cross-compilation to resource-constrained targets like DSPs, FPGAs, ASICs or WebAssembly.
GitHub repository with 15 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: C++
Topics: embedded, embedded-systems, cross-compile, google-test, asic, dsp
Streamline FPGA development with 8 Vivado/Vitis skills for HLS, RTL, synthesis, constraints, timing, and debug workflows
GitHub repository with 11 stars and 5 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: ReScript
Topics: accept-language, browser, cos, flutter, fpga, gin
Using e-graphs for logic synthesis (ICCAD'25)
GitHub repository with 35 stars and 6 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: Rust
Topics: egg, fpga, rust, verilog, yosys, rtl
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc