XuanTongYao/XT_RISC-V_Soc
一个极其简易的RV32I指令集单核MCU,用户级与特权级支持,仅运行机器模式。
GitHub repository with 60 stars and 6 forks.
Language: SystemVerilog
一个极其简易的RV32I指令集单核MCU,用户级与特权级支持,仅运行机器模式。
GitHub repository with 60 stars and 6 forks.
Language: SystemVerilog
2026-06-12: 60 stars and 6 forks.
OpenTitan: Open source silicon root of trust
GitHub repository with 3,461 stars and 1,048 forks.
Trending score: 2.26; stars gained: +11; forks gained: +0.
Language: SystemVerilog
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 50 stars and 7 forks.
Trending score: 1.05; stars gained: +7; forks gained: +0.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 407 stars and 108 forks.
Trending score: 1.03; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
GitHub repository with 19 stars and 0 forks.
Trending score: 0.60; stars gained: +2; forks gained: +0.
Language: SystemVerilog
GitHub repository with 27 stars and 1 forks.
Trending score: 0.55; stars gained: +1; forks gained: +0.
Language: SystemVerilog
EECE26 - Digital IC Design and Verification Graduation Project | Source Code
GitHub repository with 6 stars and 0 forks.
Trending score: 0.42; stars gained: +1; forks gained: +0.
Language: SystemVerilog
OpenTitan: Open source silicon root of trust
GitHub repository with 3,461 stars and 1,048 forks.
Trending score: 2.26; stars gained: +11; forks gained: +0.
Language: SystemVerilog
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 50 stars and 7 forks.
Trending score: 1.05; stars gained: +7; forks gained: +0.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 407 stars and 108 forks.
Trending score: 1.03; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
GitHub repository with 19 stars and 0 forks.
Trending score: 0.60; stars gained: +2; forks gained: +0.
Language: SystemVerilog
GitHub repository with 27 stars and 1 forks.
Trending score: 0.55; stars gained: +1; forks gained: +0.
Language: SystemVerilog
EECE26 - Digital IC Design and Verification Graduation Project | Source Code
GitHub repository with 6 stars and 0 forks.
Trending score: 0.42; stars gained: +1; forks gained: +0.
Language: SystemVerilog