Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike, shrike-devboard, shrike-fpga, shrike-lite, esp32
Trending score 0.68, activity score 0.03, stars gained +4, forks gained +0.
2026-06-05: 446 stars and 61 forks.
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc
Netlist API (and more) for EDA flow development
GitHub repository with 139 stars and 22 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: asic, cpp, eda, fpga, netlist, semiconductor
A minimal RTL implementation of llama2.c stories260K forward inference on FPGA
GitHub repository with 11 stars and 0 forks.
Trending score: 0.03; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: fpga, hardware-accelerator, llama2, llama2-c, llm, rtl
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
GitHub repository with 2,724 stars and 909 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: opendb-database, openroad, lef, verilog, timing-analysis, def
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D
GitHub repository with 7 stars and 3 forks.
Trending score: 0.50; stars gained: +2; forks gained: +1.
Language: Verilog
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc
Amiga Minimig ported to the Tang Nano 20k FPGA
GitHub repository with 194 stars and 26 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: Verilog
Netlist API (and more) for EDA flow development
GitHub repository with 139 stars and 22 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: asic, cpp, eda, fpga, netlist, semiconductor
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Digital logic design tool and simulator
GitHub repository with 7,164 stars and 950 forks.
Trending score: 1.01; stars gained: +6; forks gained: +1.
Language: Java
Topics: logisim-evolution, education, circuit, circuits, digital-circuit, digital-circuits
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
libhatchet is a fast compiling lightweight C17/C++20 bespoke alternative to the C++ standard library designed for cross-compilation to resource-constrained targets like DSPs, FPGAs, ASICs or WebAssembly.
GitHub repository with 15 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: C++
Topics: embedded, embedded-systems, cross-compile, google-test, asic, dsp
Streamline FPGA development with 8 Vivado/Vitis skills for HLS, RTL, synthesis, constraints, timing, and debug workflows
GitHub repository with 11 stars and 5 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: ReScript
Topics: accept-language, browser, cos, flutter, fpga, gin
Using e-graphs for logic synthesis (ICCAD'25)
GitHub repository with 35 stars and 6 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: Rust
Topics: egg, fpga, rust, verilog, yosys, rtl