chipsalliance/sv-tests

24h trend summary

Trending score 0.05, activity score 0.05, stars gained +0, forks gained +0.

Latest metric snapshot

2026-06-05: 378 stars and 94 forks.

Similar repositories

1. 1. chipsalliance/sv-tests

   Test suite designed to check compliance with the SystemVerilog standard.

   GitHub repository with 378 stars and 94 forks.

   Trending score: 0.05; stars gained: +0; forks gained: +0.

   Language: SystemVerilog

   Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

Trending in SystemVerilog

1. 1. fpgasystems/Coyote

   Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

   GitHub repository with 371 stars and 104 forks.

   Trending score: 1.08; stars gained: +8; forks gained: +1.

   Language: SystemVerilog

   Topics: fpga, rdma, tcp, virtualization, gpu, networking

2. 2. lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   GitHub repository with 3,427 stars and 1,035 forks.

   Trending score: 0.61; stars gained: +1; forks gained: +3.

   Language: SystemVerilog

3. 3. pavona/pavona

   A library of modular, tapeout-proven, and secure-by-default open silicon blocks

   GitHub repository with 60 stars and 13 forks.

   Trending score: 0.53; stars gained: +2; forks gained: +1.

   Language: SystemVerilog

4. 4. xlsynth/bedrock-rtl

   High quality and composable RTL libraries in SystemVerilog

   GitHub repository with 33 stars and 5 forks.

   Trending score: 0.11; stars gained: +0; forks gained: +0.

   Language: SystemVerilog

   Topics: hardware, rtl, verilog, bazel-rules, chips

5. 5. chipsalliance/sv-tests

   Test suite designed to check compliance with the SystemVerilog standard.

   GitHub repository with 378 stars and 94 forks.

   Trending score: 0.05; stars gained: +0; forks gained: +0.

   Language: SystemVerilog

   Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

6. 6. rohtakpat314/riscvcpu

   Single-cycle RISC-V 32-bit CPU

   GitHub repository with 9 stars and 0 forks.

   Trending score: 0.05; stars gained: +0; forks gained: +0.

   Language: SystemVerilog

Trending topic: systemverilog

1. 1. veryl-lang/veryl

   Veryl: A Modern Hardware Description Language

   GitHub repository with 949 stars and 63 forks.

   Trending score: 0.75; stars gained: +2; forks gained: +1.

   Language: Rust

   Topics: hdl, rtl, rust, systemverilog, verilog

2. 2. rggen/rggen

   Code generation tool for control and status registers

   GitHub repository with 461 stars and 57 forks.

   Trending score: 0.23; stars gained: +0; forks gained: +0.

   Language: Ruby

   Topics: amba, apb, asic, axi, csr, eda

3. 3. chipsalliance/sv-tests

   Test suite designed to check compliance with the SystemVerilog standard.

   GitHub repository with 378 stars and 94 forks.

   Trending score: 0.05; stars gained: +0; forks gained: +0.

   Language: SystemVerilog

   Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

4. 4. chipsalliance/Surelog

   SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

   GitHub repository with 463 stars and 82 forks.

   Trending score: 0.04; stars gained: +0; forks gained: +0.

   Language: C++

   Topics: antlr, antlr4-grammar, elaboration, linter, parser, parser-ast

5. 5. chipsalliance/UHDM

   Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

   GitHub repository with 257 stars and 42 forks.

   Trending score: 0.04; stars gained: +0; forks gained: +0.

   Language: C++

   Topics: ieee-standard, listener, serialization, systemverilog, vpi-api, vpi-interface