🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
GitHub repository with 2,142 stars and 348 forks.
Language: VHDL
Topics: asic, cpu, fpga, microcontroller, processor, risc-v, soc, soft-core, verilog, vhdl
2026-06-14: 2,142 stars and 348 forks.
VHDL 2008/93/87 simulator
GitHub repository with 2,835 stars and 415 forks.
Trending score: 0.77; stars gained: +1; forks gained: +0.
Language: VHDL
DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
GitHub repository with 193 stars and 49 forks.
Trending score: 0.73; stars gained: +1; forks gained: +0.
Language: VHDL
TurboGrafx-16 CD / PC Engine CD for MiSTer
GitHub repository with 105 stars and 63 forks.
Trending score: 0.20; stars gained: +0; forks gained: +1.
Language: VHDL
SNES for MiSTer
GitHub repository with 237 stars and 97 forks.
Trending score: 0.12; stars gained: +0; forks gained: +1.
Language: VHDL
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k Mega 138K Pro Console60k/138k FPGA
GitHub repository with 127 stars and 20 forks.
Trending score: 0.10; stars gained: +0; forks gained: +0.
Language: VHDL
Topics: fpga, tang-nano, c64, mist, commodore, gowin
GitHub repository with 5 stars and 0 forks.
Trending score: 0.09; stars gained: +0; forks gained: +0.
Language: VHDL
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
GitHub repository with 265 stars and 57 forks.
Trending score: 0.77; stars gained: +1; forks gained: +0.
Language: Python
Topics: asic, efpga, fpga, python, verilog, vhdl
Netlist API (and more) for EDA flow development
GitHub repository with 141 stars and 24 forks.
Trending score: 0.47; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: netlist, eda, semiconductor, verilog, asic, fpga
Haskell to VHDL/Verilog/SystemVerilog compiler
GitHub repository with 1,599 stars and 166 forks.
Trending score: 0.40; stars gained: +0; forks gained: +1.
Language: Haskell
Topics: haskell, hardware-description-language, fpga, vhdl, verilog, systemverilog
Modular hardware build system
GitHub repository with 1,165 stars and 127 forks.
Trending score: 0.24; stars gained: +0; forks gained: +0.
Language: Python
Topics: asic, cmos, eda, fpga, hls, make
Code generation tool for control and status registers
GitHub repository with 461 stars and 57 forks.
Trending score: 0.23; stars gained: +0; forks gained: +0.
Language: Ruby
Topics: amba, apb, asic, axi, csr, eda
An Open Source EDA Infracstructure and Tools from Netlist to GDS for ASIC Design.
GitHub repository with 9 stars and 3 forks.
Trending score: 0.10; stars gained: +0; forks gained: +0.
Language: C++
Topics: asic, cpp, eda, gds, netlist