Xilinx/XRT
Run Time for AIE and FPGA based platforms
GitHub repository with 664 stars and 537 forks.
Language: C++
Topics: fpga, xrt, linux-kernel, vitis, aie, npu, ryzen, versal, hip, ctrlcode
Run Time for AIE and FPGA based platforms
GitHub repository with 664 stars and 537 forks.
Language: C++
Topics: fpga, xrt, linux-kernel, vitis, aie, npu, ryzen, versal, hip, ctrlcode
Trending score 0.05, activity score 0.05, stars gained +0, forks gained +0.
2026-06-05: 664 stars and 537 forks.
Verilog to Routing -- Open Source CAD Flow for FPGA Research
GitHub repository with 1,238 stars and 444 forks.
Trending score: 0.53; stars gained: +2; forks gained: +1.
Language: C++
Topics: vtr, fpga, cad, verilog, placement, routing
libhatchet is a fast compiling lightweight C17/C++20 bespoke alternative to the C++ standard library designed for cross-compilation to resource-constrained targets like DSPs, FPGAs, ASICs or WebAssembly.
GitHub repository with 15 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: C++
Topics: embedded, embedded-systems, cross-compile, google-test, asic, dsp
Run Time for AIE and FPGA based platforms
GitHub repository with 664 stars and 537 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: C++
Topics: fpga, xrt, linux-kernel, vitis, aie, npu
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
GitHub repository with 238 stars and 58 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: C++
Topics: live, synthesis, fpga, asic, simulation, hdl
A lightweight high performance tensor algebra framework for modern C++
GitHub repository with 838 stars and 80 forks.
Trending score: 0.00.
Language: C++
Topics: tensors, tensor-contraction, multidimensional-arrays, simd, hpc, small-blas
LLM inference in C/C++
GitHub repository with 114,740 stars and 19,198 forks.
Trending score: 4.40; stars gained: +304; forks gained: +99.
Language: C++
Topics: ggml
DuckDB is an analytical in-process SQL database management system
GitHub repository with 38,622 stars and 3,299 forks.
Trending score: 3.50; stars gained: +40; forks gained: +6.
Language: C++
Topics: analytics, database, embedded-database, olap, sql
Community maintained hardware plugin for vLLM on Ascend
GitHub repository with 2,201 stars and 1,350 forks.
Trending score: 3.25; stars gained: +16; forks gained: +22.
Language: C++
Topics: ascend, inference, llm, llm-serving, llmops, mlops
:electron: Build cross-platform desktop apps with JavaScript, HTML, and CSS
GitHub repository with 121,543 stars and 17,235 forks.
Trending score: 3.02; stars gained: +16; forks gained: +2.
Language: C++
Topics: electron, javascript, c-plus-plus, html, css, chrome
ClickHouse® is a real-time analytics database management system
GitHub repository with 47,834 stars and 8,469 forks.
Trending score: 2.96; stars gained: +53; forks gained: +10.
Language: C++
Topics: ai, analytics, big-data, clickhouse, cloud-native, cpp
Truly independent web browser
GitHub repository with 63,772 stars and 3,077 forks.
Trending score: 2.89; stars gained: +52; forks gained: +5.
Language: C++
Topics: browser, browser-engine
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 60 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
GitHub repository with 2,123 stars and 343 forks.
Trending score: 0.65; stars gained: +3; forks gained: +1.
Language: VHDL
Topics: risc-v, soft-core, vhdl, fpga, soc, microcontroller
Verilog to Routing -- Open Source CAD Flow for FPGA Research
GitHub repository with 1,238 stars and 444 forks.
Trending score: 0.53; stars gained: +2; forks gained: +1.
Language: C++
Topics: vtr, fpga, cad, verilog, placement, routing
libhatchet is a fast compiling lightweight C17/C++20 bespoke alternative to the C++ standard library designed for cross-compilation to resource-constrained targets like DSPs, FPGAs, ASICs or WebAssembly.
GitHub repository with 15 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: C++
Topics: embedded, embedded-systems, cross-compile, google-test, asic, dsp
Modular hardware build system
GitHub repository with 1,164 stars and 127 forks.
Trending score: 0.49; stars gained: +2; forks gained: -1.
Language: Python
Topics: asic, cmos, eda, fpga, hls, make