AleksandarLilic/ama-riscv

SystemVerilog implementation of RISC-V RV32IM & custom packed SIMD ISA as 5-stage single-issue CPU core with branch predictor and L1 caches, tied up in lockstep with ISA sim over DPI for verification

GitHub repository with 7 stars and 0 forks.

Language: SystemVerilog

Topics: branch-prediction, branch-predictor, cache, cpu, custom-isa, dpi-c, isa, risc-v, riscv, rtl

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2026-06-15: 7 stars and 0 forks.

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