lowRISC/mocha
CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.
GitHub repository with 32 stars and 18 forks.
Language: SystemVerilog
CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.
GitHub repository with 32 stars and 18 forks.
Language: SystemVerilog
2026-06-05: 32 stars and 18 forks.
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
OpenTitan: Open source silicon root of trust
GitHub repository with 3,425 stars and 1,034 forks.
Trending score: 0.61; stars gained: +1; forks gained: +3.
Language: SystemVerilog
A library of modular, tapeout-proven, and secure-by-default open silicon blocks
GitHub repository with 59 stars and 13 forks.
Trending score: 0.53; stars gained: +2; forks gained: +1.
Language: SystemVerilog
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
GitHub repository with 543 stars and 523 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: SystemVerilog
High quality and composable RTL libraries in SystemVerilog
GitHub repository with 33 stars and 5 forks.
Trending score: 0.11; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: hardware, rtl, verilog, bazel-rules, chips
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 94 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
OpenTitan: Open source silicon root of trust
GitHub repository with 3,425 stars and 1,034 forks.
Trending score: 0.61; stars gained: +1; forks gained: +3.
Language: SystemVerilog
A library of modular, tapeout-proven, and secure-by-default open silicon blocks
GitHub repository with 59 stars and 13 forks.
Trending score: 0.53; stars gained: +2; forks gained: +1.
Language: SystemVerilog
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
GitHub repository with 543 stars and 523 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: SystemVerilog
High quality and composable RTL libraries in SystemVerilog
GitHub repository with 33 stars and 5 forks.
Trending score: 0.11; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: hardware, rtl, verilog, bazel-rules, chips
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 94 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing