joegrand/bsodomizer-hd-c5g
BSODomizer HD: HDL for Cyclone V GX Starter Kit
GitHub repository with 15 stars and 3 forks.
Language: SystemVerilog
BSODomizer HD: HDL for Cyclone V GX Starter Kit
GitHub repository with 15 stars and 3 forks.
Language: SystemVerilog
2026-06-13: 15 stars and 3 forks.
Verilator open-source SystemVerilog simulator and lint system
GitHub repository with 3,683 stars and 834 forks.
Trending score: 1.77; stars gained: +7; forks gained: +1.
Language: SystemVerilog
Topics: compilers, cpp, rtl, system-verilog, systemc, verilator
A library of modular, tapeout-proven, and secure-by-default open silicon blocks
GitHub repository with 66 stars and 15 forks.
Trending score: 1.34; stars gained: +2; forks gained: +0.
Language: SystemVerilog
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 32 stars and 6 forks.
Trending score: 0.95; stars gained: +8; forks gained: +5.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
GitHub repository with 14 stars and 0 forks.
Trending score: 0.83; stars gained: +5; forks gained: +0.
Language: SystemVerilog
Compact 80386 CPU in SystemVerilog
GitHub repository with 140 stars and 9 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: SystemVerilog
Verilator open-source SystemVerilog simulator and lint system
GitHub repository with 3,683 stars and 834 forks.
Trending score: 1.77; stars gained: +7; forks gained: +1.
Language: SystemVerilog
Topics: compilers, cpp, rtl, system-verilog, systemc, verilator
A library of modular, tapeout-proven, and secure-by-default open silicon blocks
GitHub repository with 66 stars and 15 forks.
Trending score: 1.34; stars gained: +2; forks gained: +0.
Language: SystemVerilog
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 32 stars and 6 forks.
Trending score: 0.95; stars gained: +8; forks gained: +5.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
GitHub repository with 14 stars and 0 forks.
Trending score: 0.83; stars gained: +5; forks gained: +0.
Language: SystemVerilog
Compact 80386 CPU in SystemVerilog
GitHub repository with 140 stars and 9 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: SystemVerilog