ellisgl/sap-1-v2-mojo

SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.

GitHub repository with 13 stars and 4 forks.

Language: Verilog

Topics: fpga, verilog, mojo-fpga-board, cpu

Open provider repository

Latest metric snapshot

2026-06-15: 13 stars and 4 forks.

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