chipsalliance/UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

GitHub repository with 257 stars and 42 forks.

Language: C++

Topics: ieee-standard, listener, serialization, systemverilog, vpi-api, vpi-interface

Open provider repository

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Trending score 0.04, activity score 0.04, stars gained +0, forks gained +0.

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2026-06-02: 257 stars and 42 forks.

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    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    GitHub repository with 257 stars and 42 forks.

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    Language: C++

    Topics: ieee-standard, listener, serialization, systemverilog, vpi-api, vpi-interface

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  1. 1. chipsalliance/UHDM

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    GitHub repository with 257 stars and 42 forks.

    Trending score: 0.04; stars gained: +0; forks gained: +0.

    Language: C++

    Topics: ieee-standard, listener, serialization, systemverilog, vpi-api, vpi-interface