chipsalliance/caliptra-rtl
HW Design Collateral for Caliptra RoT IP
GitHub repository with 139 stars and 92 forks.
Language: SystemVerilog
HW Design Collateral for Caliptra RoT IP
GitHub repository with 139 stars and 92 forks.
Language: SystemVerilog
2026-06-05: 139 stars and 92 forks.
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
OpenTitan: Open source silicon root of trust
GitHub repository with 3,427 stars and 1,035 forks.
Trending score: 0.61; stars gained: +1; forks gained: +3.
Language: SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 94 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: compliance-testing, hdl, rtl, symbiflow, systemverilog, verilog
一个极其简易的RV32I指令集单核MCU,用户级与特权级支持,仅运行机器模式。
GitHub repository with 60 stars and 6 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Baochip 1x Silicon
GitHub repository with 360 stars and 32 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
AI-native Chiplet design flow based on open-source EDA toolchain
GitHub repository with 25 stars and 3 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
OpenTitan: Open source silicon root of trust
GitHub repository with 3,427 stars and 1,035 forks.
Trending score: 0.61; stars gained: +1; forks gained: +3.
Language: SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 94 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: compliance-testing, hdl, rtl, symbiflow, systemverilog, verilog
一个极其简易的RV32I指令集单核MCU,用户级与特权级支持,仅运行机器模式。
GitHub repository with 60 stars and 6 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Baochip 1x Silicon
GitHub repository with 360 stars and 32 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
AI-native Chiplet design flow based on open-source EDA toolchain
GitHub repository with 25 stars and 3 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog