Discover trending Verilog repositories ranked by recent growth and activity.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
GitHub repository with 2,724 stars and 909 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: cpp, def, eda, gdsii, lef, opendb-database
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 445 stars and 60 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28nm.
GitHub repository with 11 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: Verilog
FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D
GitHub repository with 7 stars and 3 forks.
Trending score: 0.50; stars gained: +2; forks gained: +1.
Language: Verilog
Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and supported with comprehensive testbenches.
GitHub repository with 53 stars and 6 forks.
Trending score: 0.37; stars gained: +1; forks gained: +0.
Language: Verilog
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc
Amiga Minimig ported to the Tang Nano 20k FPGA
GitHub repository with 194 stars and 26 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: Verilog
Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)
GitHub repository with 5 stars and 0 forks.
Trending score: 0.11; stars gained: +0; forks gained: +0.
Language: Verilog
一步一步写MIPS CPU
GitHub repository with 864 stars and 161 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: mips-cpu, nscscc, verilog
The Open Source Hardware Accelerator for Efficient Neural Network Inference
GitHub repository with 55 stars and 8 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Netlist API (and more) for EDA flow development
GitHub repository with 139 stars and 22 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: netlist, eda, semiconductor, verilog, asic, fpga
A minimal RTL implementation of llama2.c stories260K forward inference on FPGA
GitHub repository with 11 stars and 0 forks.
Trending score: 0.03; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: fpga, hardware-accelerator, llama2, llama2-c, llm, rtl
An Open-Source Analog Mixed-Signal Chip Design Template & Tutorial for the ihp-sg13g2 Open-PDK
GitHub repository with 18 stars and 2 forks.
Trending score: 0.05.
Language: Verilog
GitHub repository with 177 stars and 66 forks.
Trending score: 0.05.
Language: Verilog
NeoGeo for MiSTer
GitHub repository with 170 stars and 90 forks.
Trending score: 0.05.
Language: Verilog
Sega Megadrive for MiSTer
GitHub repository with 58 stars and 25 forks.
Trending score: 0.05.
Language: Verilog
Mega CD for MiSTer
GitHub repository with 75 stars and 41 forks.
Trending score: 0.05.
Language: Verilog
Macintosh Plus for MiSTer
GitHub repository with 50 stars and 22 forks.
Trending score: 0.05.
Language: Verilog
Gameboy for MiSTer
GitHub repository with 130 stars and 59 forks.
Trending score: 0.05.
Language: Verilog
ao486 port for MiSTer
GitHub repository with 354 stars and 91 forks.
Trending score: 0.05.
Language: Verilog
Open source AI inference chip for robotics edge — transformer + training capable, GDS verified
GitHub repository with 5 stars and 1 forks.
Trending score: 0.04.
Language: Verilog