Learning-Chips-Lab/OpenEye

24h trend summary

Trending score 0.05, activity score 0.05, stars gained +0, forks gained +0.

Latest metric snapshot

2026-06-05: 55 stars and 8 forks.

Similar repositories

1. 1. The-OpenROAD-Project/OpenROAD

   OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

   GitHub repository with 2,724 stars and 908 forks.

   Trending score: 0.69; stars gained: +4; forks gained: +0.

   Language: Verilog

   Topics: cpp, def, eda, gdsii, lef, opendb-database

2. 2. vicharak-in/shrike

   Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.

   GitHub repository with 444 stars and 60 forks.

   Trending score: 0.68; stars gained: +4; forks gained: +0.

   Language: Verilog

3. 3. nova-studios-hw/novagpu-ts1t

   N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28nm.

   GitHub repository with 11 stars and 0 forks.

   Trending score: 0.50; stars gained: +2; forks gained: +0.

   Language: Verilog

4. 4. StreamCore-jiali/FPGA-AES-GCM

   FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D

   GitHub repository with 7 stars and 3 forks.

   Trending score: 0.50; stars gained: +2; forks gained: +1.

   Language: Verilog

5. 5. OpenSiliconHub/OpenSiliconHub

   Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and supported with comprehensive testbenches.

   GitHub repository with 53 stars and 6 forks.

   Trending score: 0.37; stars gained: +1; forks gained: +0.

   Language: Verilog

   Topics: chacha20, dsp, hardware-designs, keystream-generators, prngs, rabbit

6. 6. lnis-uofu/OpenFPGA

   An Open-source FPGA IP Generator

   GitHub repository with 1,109 stars and 200 forks.

   Trending score: 0.32; stars gained: +1; forks gained: +1.

   Language: Verilog

   Topics: fpga, fpga-soc

Trending in Verilog

1. 1. The-OpenROAD-Project/OpenROAD

   OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

   GitHub repository with 2,724 stars and 908 forks.

   Trending score: 0.69; stars gained: +4; forks gained: +0.

   Language: Verilog

   Topics: cpp, def, eda, gdsii, lef, opendb-database

2. 2. vicharak-in/shrike

   Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.

   GitHub repository with 444 stars and 60 forks.

   Trending score: 0.68; stars gained: +4; forks gained: +0.

   Language: Verilog

3. 3. nova-studios-hw/novagpu-ts1t

   N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28nm.

   GitHub repository with 11 stars and 0 forks.

   Trending score: 0.50; stars gained: +2; forks gained: +0.

   Language: Verilog

4. 4. StreamCore-jiali/FPGA-AES-GCM

   FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D

   GitHub repository with 7 stars and 3 forks.

   Trending score: 0.50; stars gained: +2; forks gained: +1.

   Language: Verilog

5. 5. OpenSiliconHub/OpenSiliconHub

   Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and supported with comprehensive testbenches.

   GitHub repository with 53 stars and 6 forks.

   Trending score: 0.37; stars gained: +1; forks gained: +0.

   Language: Verilog

   Topics: chacha20, dsp, hardware-designs, keystream-generators, prngs, rabbit

6. 6. lnis-uofu/OpenFPGA

   An Open-source FPGA IP Generator

   GitHub repository with 1,109 stars and 200 forks.

   Trending score: 0.32; stars gained: +1; forks gained: +1.

   Language: Verilog

   Topics: fpga, fpga-soc