Discover trending SystemVerilog repositories ranked by recent growth and activity.
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
OpenTitan: Open source silicon root of trust
GitHub repository with 3,427 stars and 1,035 forks.
Trending score: 0.61; stars gained: +1; forks gained: +3.
Language: SystemVerilog
A library of modular, tapeout-proven, and secure-by-default open silicon blocks
GitHub repository with 60 stars and 13 forks.
Trending score: 0.53; stars gained: +2; forks gained: +1.
Language: SystemVerilog
High quality and composable RTL libraries in SystemVerilog
GitHub repository with 33 stars and 5 forks.
Trending score: 0.11; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: hardware, rtl, verilog, bazel-rules, chips
Test suite designed to check compliance with the SystemVerilog standard.
GitHub repository with 378 stars and 94 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing
Single-cycle RISC-V 32-bit CPU
GitHub repository with 9 stars and 0 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: SystemVerilog
一个极其简易的RV32I指令集单核MCU，用户级与特权级支持，仅运行机器模式。
GitHub repository with 60 stars and 6 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Baochip 1x Silicon
GitHub repository with 360 stars and 32 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
AI-native Chiplet design flow based on open-source EDA toolchain
GitHub repository with 25 stars and 3 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Built an 8×8 systolic array in SystemVerilog which is the architecture behind Google's TPU. The idea is simple but the implementation is interesting: instead of repeatedly fetching weights from memory, you load them once into 64 Processing Elements and let activations flow through.
GitHub repository with 7 stars and 0 forks.
Trending score: 0.05.
Language: SystemVerilog
A Fast, Low-Overhead On-chip Network
GitHub repository with 304 stars and 63 forks.
Trending score: 0.05.
Language: SystemVerilog
GitHub repository with 137 stars and 71 forks.
Trending score: 0.05.
Language: SystemVerilog
Sega 32X implementation for MiSTer
GitHub repository with 62 stars and 26 forks.
Trending score: 0.05.
Language: SystemVerilog