kisp-nus/anvil
GitHub repository with 28 stars and 9 forks.
Language: OCaml
Topics: asic, fpga, hardware, hdl, programming-language, systemverilog, verilog
GitHub repository with 28 stars and 9 forks.
Language: OCaml
Topics: asic, fpga, hardware, hdl, programming-language, systemverilog, verilog
2026-06-05: 28 stars and 9 forks.
The core OCaml system: compilers, runtime system, base libraries
GitHub repository with 6,390 stars and 1,237 forks.
Trending score: 1.39; stars gained: +28; forks gained: +2.
Language: OCaml
Topics: compiler, functional-language, ocaml
🔎 Static code analysis engine to find security issues in code.
GitHub repository with 2,649 stars and 218 forks.
Trending score: 1.04; stars gained: +11; forks gained: +1.
Language: OCaml
Performant type-checking for python.
GitHub repository with 7,166 stars and 452 forks.
Trending score: 0.70; stars gained: +1; forks gained: +0.
Language: OCaml
Topics: abstract-interpretation, code-quality, control-flow-analysis, ocaml, program-analysis, python
MASC - Multi-Agent Streaming Coordination in OCaml
GitHub repository with 5 stars and 1 forks.
Trending score: 0.55; stars gained: +0; forks gained: +0.
Language: OCaml
A static analyzer for Java, C, C++, and Objective-C
GitHub repository with 15,635 stars and 2,092 forks.
Trending score: 0.49; stars gained: +2; forks gained: -1.
Language: OCaml
Topics: static-analysis, static-code-analysis, code-quality, java, c, cpp
Github test mirror of the Octez software. Please do not submit pull-requests here!
GitHub repository with 113 stars and 40 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: OCaml
Topics: blockchain, ocaml, smart-contracts, tezos
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
GitHub repository with 2,123 stars and 343 forks.
Trending score: 0.65; stars gained: +3; forks gained: +1.
Language: VHDL
Topics: risc-v, soft-core, vhdl, fpga, soc, microcontroller
libhatchet is a fast compiling lightweight C17/C++20 bespoke alternative to the C++ standard library designed for cross-compilation to resource-constrained targets like DSPs, FPGAs, ASICs or WebAssembly.
GitHub repository with 15 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: C++
Topics: embedded, embedded-systems, cross-compile, google-test, asic, dsp
Modular hardware build system
GitHub repository with 1,164 stars and 127 forks.
Trending score: 0.49; stars gained: +2; forks gained: -1.
Language: Python
Topics: asic, cmos, eda, fpga, hls, make
Code generation tool for control and status registers
GitHub repository with 461 stars and 57 forks.
Trending score: 0.23; stars gained: +0; forks gained: +0.
Language: Ruby
Topics: amba, apb, asic, axi, csr, eda
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
GitHub repository with 238 stars and 58 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: C++
Topics: live, synthesis, fpga, asic, simulation, hdl
Netlist API (and more) for EDA flow development
GitHub repository with 139 stars and 22 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: asic, cpp, eda, fpga, netlist, semiconductor