The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zimop Zba Zbb Zbs Zbkb Sdext Sdtrig microcontroller in VHDL
GitHub repository with 7 stars and 1 forks.
Language: C
Topics: fpga, hardware, riscv, riscv32, riscv32im, rv32im, soc, vhdl
2026-06-05: 7 stars and 1 forks.
DeepSeek 4 Flash local inference engine for Metal and CUDA
GitHub repository with 13,009 stars and 1,133 forks.
Trending score: 3.46; stars gained: +74; forks gained: +5.
Language: C
The programming language for agents
GitHub repository with 4,877 stars and 315 forks.
Trending score: 2.75; stars gained: +27; forks gained: +4.
Language: C
ESP32 desk dashboard that shows Claude Code usage
GitHub repository with 1,538 stars and 184 forks.
Trending score: 2.63; stars gained: +24; forks gained: +5.
Language: C
Recent CVE PoC & reproduction scripts. Focused on high-severity vulnerabilities across Linux kernel, Windows, macOS and more.
GitHub repository with 493 stars and 84 forks.
Trending score: 2.27; stars gained: +20; forks gained: +2.
Language: C
Topics: c, cybersecurity, linux, poc, python, python3
Real-time 3D full-body reconstruction from a single camera, Multiperson BVH output, Pure C++ runtime, ONNX + ggml, 70-joint skeleton with hands.
GitHub repository with 475 stars and 62 forks.
Trending score: 1.78; stars gained: +2; forks gained: +1.
Language: C
Topics: 3d-human-pose, bvh, computer-vision, cpp, cuda, ggml
GitHub repository with 4,817 stars and 774 forks.
Trending score: 1.65; stars gained: +6; forks gained: -2.
Language: C
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 371 stars and 104 forks.
Trending score: 1.08; stars gained: +8; forks gained: +1.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
libhatchet is a fast compiling lightweight C17/C++20 bespoke alternative to the C++ standard library designed for cross-compilation to resource-constrained targets like DSPs, FPGAs, ASICs or WebAssembly.
GitHub repository with 15 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: C++
Topics: embedded, embedded-systems, cross-compile, google-test, asic, dsp
Streamline FPGA development with 8 Vivado/Vitis skills for HLS, RTL, synthesis, constraints, timing, and debug workflows
GitHub repository with 11 stars and 5 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: ReScript
Topics: accept-language, browser, cos, flutter, fpga, gin
Using e-graphs for logic synthesis (ICCAD'25)
GitHub repository with 35 stars and 6 forks.
Trending score: 0.33; stars gained: +1; forks gained: +0.
Language: Rust
Topics: egg, fpga, rust, verilog, yosys, rtl
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc