fpgasystems/libstf

Hardware library for data processing (supports the Coyote FPGA shell)

GitHub repository with 6 stars and 6 forks.

Language: SystemVerilog

Open provider repository

Latest metric snapshot

2026-06-05: 6 stars and 6 forks.

Similar repositories

  1. 1. fpgasystems/Coyote

    Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

    GitHub repository with 371 stars and 104 forks.

    Trending score: 1.08; stars gained: +8; forks gained: +1.

    Language: SystemVerilog

    Topics: fpga, rdma, tcp, virtualization, gpu, networking

  2. 2. lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    GitHub repository with 3,425 stars and 1,034 forks.

    Trending score: 0.61; stars gained: +1; forks gained: +3.

    Language: SystemVerilog

  3. 3. pavona/pavona

    A library of modular, tapeout-proven, and secure-by-default open silicon blocks

    GitHub repository with 59 stars and 13 forks.

    Trending score: 0.53; stars gained: +2; forks gained: +1.

    Language: SystemVerilog

  4. 4. xlsynth/bedrock-rtl

    High quality and composable RTL libraries in SystemVerilog

    GitHub repository with 33 stars and 5 forks.

    Trending score: 0.11; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: hardware, rtl, verilog, bazel-rules, chips

  5. 5. chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    GitHub repository with 378 stars and 94 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

  6. 6. rohtakpat314/riscvcpu

    Single-cycle RISC-V 32-bit CPU

    GitHub repository with 9 stars and 0 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

Trending in SystemVerilog

  1. 1. fpgasystems/Coyote

    Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

    GitHub repository with 371 stars and 104 forks.

    Trending score: 1.08; stars gained: +8; forks gained: +1.

    Language: SystemVerilog

    Topics: fpga, rdma, tcp, virtualization, gpu, networking

  2. 2. lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    GitHub repository with 3,425 stars and 1,034 forks.

    Trending score: 0.61; stars gained: +1; forks gained: +3.

    Language: SystemVerilog

  3. 3. pavona/pavona

    A library of modular, tapeout-proven, and secure-by-default open silicon blocks

    GitHub repository with 59 stars and 13 forks.

    Trending score: 0.53; stars gained: +2; forks gained: +1.

    Language: SystemVerilog

  4. 4. xlsynth/bedrock-rtl

    High quality and composable RTL libraries in SystemVerilog

    GitHub repository with 33 stars and 5 forks.

    Trending score: 0.11; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: hardware, rtl, verilog, bazel-rules, chips

  5. 5. chipsalliance/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    GitHub repository with 378 stars and 94 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog

    Topics: systemverilog, symbiflow, verilog, hdl, rtl, compliance-testing

  6. 6. rohtakpat314/riscvcpu

    Single-cycle RISC-V 32-bit CPU

    GitHub repository with 9 stars and 0 forks.

    Trending score: 0.05; stars gained: +0; forks gained: +0.

    Language: SystemVerilog