DHRUT-V :- In-order superscalar RV32I RISC-V processor core written in SystemVerilog and Verified using cocotb+pyUVM. Built for education, verification, and hardware exploration. (Can it run Doom? it will)
GitHub repository with 9 stars and 2 forks.
Language: Verilog
2026-06-05: 9 stars and 2 forks.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
GitHub repository with 2,724 stars and 909 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: opendb-database, openroad, lef, verilog, timing-analysis, def
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D
GitHub repository with 7 stars and 3 forks.
Trending score: 0.50; stars gained: +2; forks gained: +1.
Language: Verilog
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc
Amiga Minimig ported to the Tang Nano 20k FPGA
GitHub repository with 194 stars and 26 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: Verilog
Netlist API (and more) for EDA flow development
GitHub repository with 139 stars and 22 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: asic, cpp, eda, fpga, netlist, semiconductor
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
GitHub repository with 2,724 stars and 909 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: opendb-database, openroad, lef, verilog, timing-analysis, def
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 446 stars and 61 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D
GitHub repository with 7 stars and 3 forks.
Trending score: 0.50; stars gained: +2; forks gained: +1.
Language: Verilog
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc
Amiga Minimig ported to the Tang Nano 20k FPGA
GitHub repository with 194 stars and 26 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: Verilog
Netlist API (and more) for EDA flow development
GitHub repository with 139 stars and 22 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: Verilog
Topics: asic, cpp, eda, fpga, netlist, semiconductor