xprova/netlist-graph
Java library for parsing and manipulating graph representations of gate-level Verilog netlists
GitHub repository with 15 stars and 8 forks.
Language: Java
Topics: verilog, parser, graphs
Java library for parsing and manipulating graph representations of gate-level Verilog netlists
GitHub repository with 15 stars and 8 forks.
Language: Java
Topics: verilog, parser, graphs
2026-06-05: 15 stars and 8 forks.
Digital logic design tool and simulator
GitHub repository with 7,164 stars and 950 forks.
Trending score: 1.01; stars gained: +6; forks gained: +1.
Language: Java
Topics: logisim-evolution, education, circuit, circuits, digital-circuit, digital-circuits
Multi-platform SDK for integrating GitHub Copilot Agent into apps and services
GitHub repository with 9,020 stars and 1,213 forks.
Trending score: 3.47; stars gained: +166; forks gained: +12.
Language: Java
Light, fluffy, and always free - The AWS Local Emulator alternative
GitHub repository with 13,633 stars and 1,294 forks.
Trending score: 3.33; stars gained: +78; forks gained: +7.
Language: Java
Topics: aws, aws-emulation, devops, docker, ec2, ecs
WebHomeTV 基于FongMi二次开发,增强了 WebHome 自定义首页、App Native SDK、网盘链接检测 和 Nostr推荐首页。 这个项目的核心目标是让 CSP 站点首页可以变成一个真正可开发的网页应用:开发者可以用 HTML/CSS/JavaScript 定制首页,再通过 App 暴露的 Native 能力完成搜索、播放、跨域请求、资源代理、最近观看、网盘检测和状态同步。
GitHub repository with 360 stars and 107 forks.
Trending score: 3.29; stars gained: +83; forks gained: +16.
Language: Java
AI equity research agent with resilient workflows, Redis Lua single-flight, pgvector RAG, versioned reports, evidence tracing, and RAG evaluation.
GitHub repository with 978 stars and 57 forks.
Trending score: 3.24; stars gained: +77; forks gained: +1.
Language: Java
Topics: ai-agent, financial-research, llm-evaluation, pgvector, postgresql, rabbitmq
Free universal database tool and SQL client
GitHub repository with 50,399 stars and 4,220 forks.
Trending score: 3.22; stars gained: +37; forks gained: +10.
Language: Java
Topics: sql, database, dbeaver, gui, mysql, postgresql
GitHub repository with 731 stars and 105 forks.
Trending score: 2.98; stars gained: +53; forks gained: +7.
Language: Java
Digital logic design tool and simulator
GitHub repository with 7,164 stars and 950 forks.
Trending score: 1.01; stars gained: +6; forks gained: +1.
Language: Java
Topics: logisim-evolution, education, circuit, circuits, digital-circuit, digital-circuits
Veryl: A Modern Hardware Description Language
GitHub repository with 949 stars and 63 forks.
Trending score: 0.75; stars gained: +2; forks gained: +1.
Language: Rust
Topics: hdl, rtl, rust, systemverilog, verilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
GitHub repository with 2,724 stars and 908 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: cpp, def, eda, gdsii, lef, opendb-database
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
GitHub repository with 2,122 stars and 343 forks.
Trending score: 0.65; stars gained: +3; forks gained: +1.
Language: VHDL
Topics: risc-v, soft-core, vhdl, fpga, soc, microcontroller
Verilog to Routing -- Open Source CAD Flow for FPGA Research
GitHub repository with 1,238 stars and 444 forks.
Trending score: 0.53; stars gained: +2; forks gained: +1.
Language: C++
Topics: cad, eda, fpga, placement, routing, synthesis
Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and supported with comprehensive testbenches.
GitHub repository with 53 stars and 6 forks.
Trending score: 0.37; stars gained: +1; forks gained: +0.
Language: Verilog
Topics: chacha20, dsp, hardware-designs, keystream-generators, prngs, rabbit