nickg/nvc
VHDL compiler and simulator
GitHub repository with 837 stars and 115 forks.
Language: C
Topics: vhdl, simulator, compiler, fpga, verilog
VHDL compiler and simulator
GitHub repository with 837 stars and 115 forks.
Language: C
Topics: vhdl, simulator, compiler, fpga, verilog
Trending score 0.38, freshness score 0.79, stars gained +0, forks gained +0.
2026-06-15: 837 stars and 115 forks.
VHDL compiler and simulator
GitHub repository with 837 stars and 115 forks.
Trending score: 0.38; stars gained: +0; forks gained: +0.
Language: C
Topics: vhdl, simulator, compiler, fpga, verilog
Microsoft PowerToys is a collection of utilities that supercharge productivity and customization on Windows
GitHub repository with 134,941 stars and 8,101 forks.
Trending score: 4.89; stars gained: +547; forks gained: +31.
Language: C
Topics: advanced-paste, color-picker, command-palette, desktop, fancyzones, keyboard-manager
Display and control your Android device
GitHub repository with 143,575 stars and 13,237 forks.
Trending score: 4.83; stars gained: +701; forks gained: +57.
Language: C
Topics: android, c, sdl2, libav, ffmpeg, screen
DeepSeek 4 Flash and PRO local inference engine for Metal, CUDA and ROCm
GitHub repository with 13,904 stars and 1,223 forks.
Trending score: 4.72; stars gained: +450; forks gained: +41.
Language: C
Linux kernel source tree
GitHub repository with 236,472 stars and 62,714 forks.
Trending score: 3.79; stars gained: +189; forks gained: +14.
Language: C
Mirror of https://git.ffmpeg.org/ffmpeg.git
GitHub repository with 61,132 stars and 13,907 forks.
Trending score: 3.64; stars gained: +77; forks gained: +3.
Language: C
Topics: audio, c, ffmpeg, fft, hevc, hls
tmux source code
GitHub repository with 46,579 stars and 2,695 forks.
Trending score: 3.37; stars gained: +50; forks gained: +2.
Language: C
cocotb: Python-based chip (RTL) verification
GitHub repository with 2,408 stars and 648 forks.
Trending score: 1.49; stars gained: +3; forks gained: +0.
Language: Python
Topics: python, test, uvm, verification, verilog, vhdl
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
GitHub repository with 265 stars and 57 forks.
Trending score: 0.77; stars gained: +1; forks gained: +0.
Language: Python
Topics: asic, efpga, fpga, python, verilog, vhdl
Haskell to VHDL/Verilog/SystemVerilog compiler
GitHub repository with 1,599 stars and 166 forks.
Trending score: 0.40; stars gained: +0; forks gained: +1.
Language: Haskell
Topics: haskell, hardware-description-language, fpga, vhdl, verilog, systemverilog
VHDL compiler and simulator
GitHub repository with 837 stars and 115 forks.
Trending score: 0.38; stars gained: +0; forks gained: +0.
Language: C
Topics: vhdl, simulator, compiler, fpga, verilog
Modular hardware build system
GitHub repository with 1,165 stars and 127 forks.
Trending score: 0.24; stars gained: +0; forks gained: +0.
Language: Python
Topics: asic, cmos, eda, fpga, hls, make
Code generation tool for control and status registers
GitHub repository with 461 stars and 57 forks.
Trending score: 0.23; stars gained: +0; forks gained: +0.
Language: Ruby
Topics: amba, apb, asic, axi, csr, eda