chiggs/oc_jpegencode
Fork of OpenCores jpegencode with Cocotb testbench
GitHub repository with 46 stars and 11 forks.
Language: Verilog
Fork of OpenCores jpegencode with Cocotb testbench
GitHub repository with 46 stars and 11 forks.
Language: Verilog
2026-06-05: 46 stars and 11 forks.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
GitHub repository with 2,724 stars and 909 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: cpp, def, eda, gdsii, lef, opendb-database
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 445 stars and 60 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28nm.
GitHub repository with 11 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: Verilog
FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D
GitHub repository with 7 stars and 3 forks.
Trending score: 0.50; stars gained: +2; forks gained: +1.
Language: Verilog
Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and supported with comprehensive testbenches.
GitHub repository with 53 stars and 6 forks.
Trending score: 0.37; stars gained: +1; forks gained: +0.
Language: Verilog
Topics: chacha20, dsp, hardware-designs, keystream-generators, prngs, rabbit
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
GitHub repository with 2,724 stars and 909 forks.
Trending score: 0.69; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: cpp, def, eda, gdsii, lef, opendb-database
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
GitHub repository with 445 stars and 60 forks.
Trending score: 0.68; stars gained: +4; forks gained: +0.
Language: Verilog
Topics: fpga, fpga-board, open-source, opensource-projects, opensource-toolchain, shrike
N.E.O.N. Architecture — Open source GPU RTL in Verilog. Token dataflow, hardware ray tracing, frame generation. First silicon target: 28nm.
GitHub repository with 11 stars and 0 forks.
Trending score: 0.50; stars gained: +2; forks gained: +0.
Language: Verilog
FPGA AES-GCM IP Core: 32 Gbps @ 250 MHz, APB3 + AXI-Stream, AES-128/192/256, NIST SP 800-38D
GitHub repository with 7 stars and 3 forks.
Trending score: 0.50; stars gained: +2; forks gained: +1.
Language: Verilog
Implementation of hardware cores—including encryption, PRNGs, DSP modules, and accelerators—developed in pure Verilog for reference. Each design is validated against official specifications and supported with comprehensive testbenches.
GitHub repository with 53 stars and 6 forks.
Trending score: 0.37; stars gained: +1; forks gained: +0.
Language: Verilog
Topics: chacha20, dsp, hardware-designs, keystream-generators, prngs, rabbit
An Open-source FPGA IP Generator
GitHub repository with 1,109 stars and 200 forks.
Trending score: 0.32; stars gained: +1; forks gained: +1.
Language: Verilog
Topics: fpga, fpga-soc