BBot! An open source, wireless beer serving robot reference design featuring a C++ program running on a BeagleBone Black, a .Net WPF control GUI and even low level FPGA integration!
GitHub repository with 20 stars and 4 forks.
Language: VHDL
2026-06-05: 20 stars and 4 forks.
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
GitHub repository with 2,122 stars and 343 forks.
Trending score: 0.65; stars gained: +3; forks gained: +1.
Language: VHDL
Network Development Kit (NDK) for FPGA cards with example application
GitHub repository with 96 stars and 16 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: VHDL
Topics: ethernet, fpga, liberouter, vhdl, network-development-kit
Sharp X68000 for MiSTer
GitHub repository with 73 stars and 33 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: VHDL
SNES for MiSTer
GitHub repository with 237 stars and 96 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: VHDL
Linux Capable 32-bit RISC-V based SoC in System Verilog
GitHub repository with 59 stars and 20 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: VHDL
A faust-to-fpga compiler toolchain
GitHub repository with 124 stars and 10 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: VHDL
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
GitHub repository with 2,122 stars and 343 forks.
Trending score: 0.65; stars gained: +3; forks gained: +1.
Language: VHDL
Network Development Kit (NDK) for FPGA cards with example application
GitHub repository with 96 stars and 16 forks.
Trending score: 0.32; stars gained: +1; forks gained: +0.
Language: VHDL
Topics: ethernet, fpga, liberouter, vhdl, network-development-kit
Sharp X68000 for MiSTer
GitHub repository with 73 stars and 33 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: VHDL
SNES for MiSTer
GitHub repository with 237 stars and 96 forks.
Trending score: 0.05; stars gained: +0; forks gained: +0.
Language: VHDL
Linux Capable 32-bit RISC-V based SoC in System Verilog
GitHub repository with 59 stars and 20 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: VHDL
A faust-to-fpga compiler toolchain
GitHub repository with 124 stars and 10 forks.
Trending score: 0.04; stars gained: +0; forks gained: +0.
Language: VHDL