shaos/retro-v

Retro-V is a SoftCPU in Verilog that implements RISC-V 32-bit architecture RV32I, but with 8-bit external bus

GitLab repository with 5 stars and 1 forks.

Language: Verilog

Topics: 32-bit, 8-bit, RISC-V, RV32I, retro

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