riscv-non-isa/riscv-ras-eri

The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors, and configuration.

GitHub repository with 11 stars and 7 forks.

Language: TeX

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2026-06-15: 11 stars and 7 forks.

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