A comprehensive framework for analyzing, and comparing different Error Correction Code (ECC) implementations with support for hardware verification, detailed performance analysis, and parallel processing capabilities.
GitHub repository with 5 stars and 2 forks.
Language: Verilog
2026-06-15: 5 stars and 2 forks.
GitHub repository with 2,097 stars and 491 forks.
Trending score: 2.76; stars gained: +37; forks gained: +2.
Language: Verilog
Full Transformer into a custom chip. microGPT in RTL, generating names on a Virtex-5 FPGA at ~56k tokens/second.
GitHub repository with 276 stars and 55 forks.
Trending score: 1.94; stars gained: +56; forks gained: +11.
Language: Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
GitHub repository with 654 stars and 500 forks.
Trending score: 1.39; stars gained: +3; forks gained: +0.
Language: Verilog
Topics: eda, rtl, tcl, def, gdsii, verilog
HDL libraries and projects
GitHub repository with 1,946 stars and 1,663 forks.
Trending score: 1.21; stars gained: +3; forks gained: +2.
Language: Verilog
Topics: analog-devices, fpga, hacktoberfest, hdl, jesd204b, verilog
z386 MiSTer core
GitHub repository with 38 stars and 1 forks.
Trending score: 0.98; stars gained: +2; forks gained: +0.
Language: Verilog
LEC - Logic Equivalence Checking - Formal Verification
GitHub repository with 44 stars and 6 forks.
Trending score: 0.59; stars gained: +2; forks gained: +0.
Language: Verilog
GitHub repository with 2,097 stars and 491 forks.
Trending score: 2.76; stars gained: +37; forks gained: +2.
Language: Verilog
Full Transformer into a custom chip. microGPT in RTL, generating names on a Virtex-5 FPGA at ~56k tokens/second.
GitHub repository with 276 stars and 55 forks.
Trending score: 1.94; stars gained: +56; forks gained: +11.
Language: Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
GitHub repository with 654 stars and 500 forks.
Trending score: 1.39; stars gained: +3; forks gained: +0.
Language: Verilog
Topics: eda, rtl, tcl, def, gdsii, verilog
HDL libraries and projects
GitHub repository with 1,946 stars and 1,663 forks.
Trending score: 1.21; stars gained: +3; forks gained: +2.
Language: Verilog
Topics: analog-devices, fpga, hacktoberfest, hdl, jesd204b, verilog
z386 MiSTer core
GitHub repository with 38 stars and 1 forks.
Trending score: 0.98; stars gained: +2; forks gained: +0.
Language: Verilog
LEC - Logic Equivalence Checking - Formal Verification
GitHub repository with 44 stars and 6 forks.
Trending score: 0.59; stars gained: +2; forks gained: +0.
Language: Verilog