Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k Mega 138K Pro Console60k/138k FPGA
GitHub repository with 127 stars and 20 forks.
Language: VHDL
Topics: fpga, tang-nano, c64, mist, commodore, gowin, tang-nano-20k, tang-primer-25k
Trending score 0.10, freshness score 0.97, stars gained +0, forks gained +0.
2026-06-15: 127 stars and 20 forks.
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k Mega 138K Pro Console60k/138k FPGA
GitHub repository with 127 stars and 20 forks.
Trending score: 0.10; stars gained: +0; forks gained: +0.
Language: VHDL
Topics: fpga, tang-nano, c64, mist, commodore, gowin
VHDL 2008/93/87 simulator
GitHub repository with 2,835 stars and 415 forks.
Trending score: 0.77; stars gained: +1; forks gained: +0.
Language: VHDL
DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
GitHub repository with 193 stars and 49 forks.
Trending score: 0.73; stars gained: +1; forks gained: +0.
Language: VHDL
TurboGrafx-16 CD / PC Engine CD for MiSTer
GitHub repository with 105 stars and 63 forks.
Trending score: 0.20; stars gained: +0; forks gained: +1.
Language: VHDL
SNES for MiSTer
GitHub repository with 237 stars and 97 forks.
Trending score: 0.12; stars gained: +0; forks gained: +1.
Language: VHDL
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k Mega 138K Pro Console60k/138k FPGA
GitHub repository with 127 stars and 20 forks.
Trending score: 0.10; stars gained: +0; forks gained: +0.
Language: VHDL
Topics: fpga, tang-nano, c64, mist, commodore, gowin
GitHub repository with 5 stars and 0 forks.
Trending score: 0.09; stars gained: +0; forks gained: +0.
Language: VHDL
Build your hardware, easily!
GitHub repository with 3,947 stars and 727 forks.
Trending score: 2.12; stars gained: +13; forks gained: +2.
Language: Python
Topics: fpga, hardware, system-on-chip
HDL libraries and projects
GitHub repository with 1,946 stars and 1,663 forks.
Trending score: 1.21; stars gained: +3; forks gained: +2.
Language: Verilog
Topics: analog-devices, fpga, hacktoberfest, hdl, jesd204b, verilog
Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.
GitHub repository with 50 stars and 7 forks.
Trending score: 1.05; stars gained: +7; forks gained: +0.
Language: SystemVerilog
Topics: computer-architecture, contest, cpu, digital-design, education, fpga
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
GitHub repository with 406 stars and 108 forks.
Trending score: 1.03; stars gained: +0; forks gained: +0.
Language: SystemVerilog
Topics: fpga, rdma, tcp, virtualization, gpu, networking
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
GitHub repository with 265 stars and 57 forks.
Trending score: 0.77; stars gained: +1; forks gained: +0.
Language: Python
Topics: asic, efpga, fpga, python, verilog, vhdl
AEE governance CLI for AI-assisted dev — WI lifecycle (specsmith wi), preflight gates, multi-agent dispatch, requirements<->test traceability, ESDB, MCP server, compliance, 64 project types (incl. brief-lang v0.14.0), 1558 tests, and 131 skills.
GitHub repository with 8 stars and 0 forks.
Trending score: 0.64; stars gained: +1; forks gained: +0.
Language: Python
Topics: aee, agentic-ai, ai-governance, applied-epistemic-engineering, cli, compliance