Entropify/Entropic_R32-P5_RISC-V
5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, ASIC-flowed, FPGA synthesized
GitHub repository with 23 stars and 0 forks.
Language: Python
Topics: 5-stage-pipeline, asic, branch-prediction, cocotb, cpu-architecture, fpga, gcc, gdsii, hazard-detection, openlane2