Axesand12310/ddr-resocket-multichannel-dma
Open-source multi-channel DDR DMA controller for FPGA: 4 write channels, 5 read channels, async FIFOs, address generation, and arbitration.
GitHub repository with 85 stars and 0 forks.
Topics: adc, awg, axi4, clc, cmp, ddr, dma, dspic, eclypse-z7, encoder